CFP: IEEE TETCI Special Issue on New Trends in Smart Chips & Smart Hardware (Aug 1)

I. AIM AND SCOPE

A special issue of the IEEE Transactions on Emerging Topics in Computational Intelligence will be dedicated to New Trends in Smart Chips and Smart Hardware. Original unpublished research and application contributions matching the main theme of this special issue are welcome. Comprehensive tutorial and survey papers on smart chips and smart hardware are considered for this special issue as well.

Machine learning and computational intelligence have attracted intensive attention in the past years. Although machine learning applications (especially those based on deep learning techniques) have been widely explored and deployed successfully recently, most applications and implementations are based on large number of training data, intensive human intervention, awful offline training time and expensive computing environment (especially in cloud servers). This is indeed in contrast to biological learning especially human brains which usually requires less data, no parameters tuning, fast online learning speed and lower computational power. These may also hinder the potential wide deployment of machine learning hardware in Internet of Things (IoT). Low power and low latency smart chips and smart hardware may finally make wide type of things become intelligent things in IoT, and thus enable us move into the new era of pervasive learning and pervasive intelligence. Recent progress in machine learning theory, biological learning, neuroscience, CMOS and post-CMOS devices (e.g, memristive devices) could have a significant impact on smart chips and smart hardware for machine learning and computational intelligence.

II. THEMES

This special issue seeks to promote novel research investigations in smart chips and smart hardware for machine learning and biologically plausible learning. Topics of interest for this special issue include, but are not limited to:

Smart Chips and Hardware:
o Hardware acceleration techniques (e.g., FPGA and ASIC) for neural and machine learning paradigms
o Neuromorphic implementation
o Learning on chips for regression, classification, feature learning and sparse coding
o Approximated and incremental computing hardware for machine learning
o Hardware implementation for cortical systems o Hardware implementation for auditory systems
o Hardware implementation for visual systems
o Artificial biological alike neurons and synapses
o Smart materials for machine and biological learning

Applications:
o Smart chips and hardware based video analytics
o Smart chips and hardware based image processing
o Smart chips and hardware based robots and UAVs

III. SUBMISSIONS

Potential authors may submit their full-length manuscripts for publication consideration through the journal manuscript submission system https://mc.manuscriptcentral.com/tetciieee. All the submissions will go through rigorous peer review.

IV. IMPORTANT DATES

Submission deadline: August 1, 2017
Author notification: October 1, 2017
Revision: December 1, 2017
Final version: January 1, 2018

V. GUEST EDITORS

Guang-Bin Huang Nanyang Technological University, Singapore egbhuang@ntu.edu.sg
Evangelos S Eleftheriou IBM Zurich Research Laboratory, Switzerland ele@zurich.ibm.com
Dhireesha Kudithipudi Rochester Institute of Technology, USA dxkeec@rit.edu
Jonathan Tapson Western Sydney University, Australia J.Tapson@westernsydney.edu.au
Hao Yu Nanyang Technological University, Singapore haoyu@ntu.edu.sg